The present invention is directed to a memory regulator system and, more particularly, to a memory regulator system having a test mode.
Modern print heads often include a memory device (i.e., a memory array) located directly on the print head. Such print head memory arrays are designed to store various bits of information that assist in providing an efficient and user-friendly printer operation. For example, the print head memory array may store information such as the type of ink/toner cartridge, type of printer, amount of ink/toner used, diagnostic data and the like.
One such print head memory array is a floating gate memory array utilizing CMOS EPROM technology. The floating gate memory array may include a two-dimensional array of memory elements or cells, wherein each cell may be programmed to store data.
The memory array may operate as follows. Initially, each cell is in its native (i.e., unprogrammed) state and therefore corresponds to a digital “0.” The cell is programmed by converting the digital “0” into a digital “1” when a sufficient voltage (e.g., 10 volts) is applied to the cell. Thus, data may be stored to the memory array by selectively programming cells in the array (i.e., the “write” mode). During a “read” mode, data may be retrieved from the memory array by applying a second voltage to the cell (e.g., 2.5 volts). The second voltage is not sufficient to write (or program the cell), but is sufficient to generate a current within the cell. The amount of current generated is measured and indicates whether or not the cell has been programmed (i.e., whether the cell is a “1” or a “0”). A small current (e.g., 5 milliamps) may correspond to the cell not being programmed and a large current (e.g., 100 milliamps) may correspond to the cell being programmed.
The printer may toggle between the write mode and the read mode by applying various voltages (e.g., 2.5 volts versus 10 volts) to the cells in the array. Accordingly, there is a need for a memory regulator system capable of supplying at least one voltage that corresponds to a read mode and a second voltage that corresponds to a write mode. Furthermore, there is a need for a memory regulator system having a test mode.